1. Field of the Invention
The present invention relates to a tape package technique and, more particularly, to a tape wiring substrate with improved EMI noise characteristic and a tape package using the same.
This U.S. non-provisional application claims benefit of priority under 35 U.S.C. §119 of Korean Patent Application No. 2006-29662, filed on Mar. 31, 2006, the entire contents of which are incorporated herein by reference.
2. Description of the Related Art
With the development of the flat display industry (e.g., LCDs for portable phones, TFT LCDs for computers and PDPs for domestic use) tape packaging, which is a component of flat display devices, is a technology that is continually evolving. As the flat display devices decrease in size, the respective tape packaging requires ever finer pitch of wiring patterns.
Tape packages may use a tape wiring substrate, and include tape carrier packages (TCPs) and chip on film (COF) packages. The TCPs may include a tape wiring substrate having a window and a semiconductor chip mounted on the tape wiring substrate using an inner lead bonding method. The COF packages may include a solid tape wiring substrate and a semiconductor chip mounted on the tape wiring substrate using a flip-chip bonding method.
In the COF packages, input/output terminal patterns may act as external connection terminals, as opposed to solder balls. The input/output terminal patterns may be directly attached to a printed circuit board or a display panel. The input/output terminal patterns may include inner leads formed at one end and outer leads formed at the other end.
FIG. 1 is a plan view of a conventional tape package 100. FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1. As shown in FIGS. 1 and 2, the COF package 100 may include a tape wiring substrate 40 and a semiconductor chip 10 that is “flip-chip” bonded to the tape wiring substrate 40 using electrode bumps 16 and 17. An encapsulant 50 may be used to seal the flip-chip bonded portions between the semiconductor chip 10 and the tape wiring substrate 40. The electrode bumps 16 and 17 may be used for input or output signals.
The electrode bumps 16 and 17 may be provided at a peripheral region of an active surface 12 of the semiconductor chip 10 at irregular intervals. The peripheral region of the active surface 12 of the semiconductor chip 10 may include an occupied region 13 where the electrode bumps 16 and 17 are provided, and an unoccupied region 14 where the electrode bumps 16 and 17 are not provided. The width of the unoccupied region 14 may be equal to or larger than the pitch of the electrode bumps 16 and 17.
The unoccupied region 14 may include a first unoccupied region 14a and a second unoccupied region 14b. The first unoccupied region 14a may be used to provide circuit wirings connecting the input bumps 16, and the second unoccupied region 14b may be used to provide circuit wirings connecting the output bumps 17 to test pads (not shown). The first unoccupied region 14a may be provided in the arrangement of the input bumps 16 and the second unoccupied region 14b may be provided in the arrangement of the output bumps 17. The test pads may be provided in scribe lines (not shown), i.e. areas formed between adjacent semiconductor chips.
The tape wiring substrate 40 may include a base film 20 and wiring patterns 31 and 33 provided on the base film 20. The tape wiring substrate 40 may have a wiring region 23 where the wiring patterns 31 and 33 are provided, and a non-wiring region 25 where the wiring patterns 31 and 33 are not provided. The wiring region 23 may correspond to the occupied region 13 of the semiconductor chip 10, and the non-wiring region 25 may correspond to the unoccupied region 14 of the semiconductor chip 10.
When the semiconductor chip 10 is bonded to the tape wiring substrate 40, the tape wiring substrate 40 may be deformed at the non-wiring region 25 due to thermal stresses. As a result, the input/output wiring patterns 31 and 33 near the non-wiring region 25 may be dislocated, thus leading to incorrect bonding between the input/output wiring patterns 31 and 33 and the electrode bumps 16 and 17, respectively. A wider non-wiring region 25 and finer pitches of the input/output wiring patterns 31 and 33 may result in more poor bonding faults. As shown in FIG. 2, the output wiring pattern 33 near the non-wiring region 25 may move toward the unoccupied region 14, for example distance (d1) becoming smaller than distance (d2).
To solve this problem, a semiconductor chip may have dummy bumps provided at an unoccupied region while a complementary tape wiring substrate may have respective dummy wiring patterns provided at a non-wiring region for bonding to the dummy bumps.
Although the conventional art is generally thought to provide acceptable performance, it is not without shortcomings. For example, in actual practice dummy bumps may be not connected to internal circuit wirings of a semiconductor chip and dummy wiring patterns may be not connected to input/output wiring patterns. Either situation can result in deteriorated EMI noise characteristics.